Design for Testability (DfT) is fundamental to digital system design. In modern chips, the handling of high volumes of test data requires the integration of test access and control structures for logic, cores, memory and interfaces. A variety of test strategies must be supported through these structures to ensure manufacturability. Defects in nanometer devices and interconnect infrastructure are caught and variability in process is handled to prevent yield problems. The move to Built-in Self-Test continues and the emergence of 3D systems is becoming clearly visible. Both presents new challenges to the design and test communities.

The first part of this course will focus on the basic knowledge needed to be effective as Design for Test engineers. The trends in Test Engineering will be discussed with specific reference to the International Technology Roadmap for Semiconductors and the iNemi roadmap. The basics of test will be covered, including fault models and test methods. The basic legacy DfT architectures, that today’s DfT techniques are based upon, are covered. The application of these basic architectures to SoC test will then be discussed including DfT structures used to support at-speed and delay testing and memory test. Built-in Self-Test will be addressed in detail.

The second part will focus on the use of IEEE standards to SoC and SiP designs and in particular the implications of nanometer design and 3D integration on the use of these standards to deliver high quality and economic test programs. A practical session will be included to instruct students on the integration of test wrappers for embedded cores. IEEE 1149, 1500 and emerging standards including 1687 will be addressed together with IEEE 1149 extensions. Variability in modern processes and the implications on test will also be addressed as will practical test issues including signal coupling, noise and instrumentation awareness.

What You Will Learn

• Process awareness – source of failures and degradation.
• Fundamentals of measurement techniques (generating and capturing continuous and sampled data).
• Extended design rules for transistor level design and layout.
• Bespoke test strategies for mixed signal functions.
• Design for testability functions at macro and systems levels of the design hierarchy.
• Fault simulation and Failure Mode and Effect Analysis techniques (FMEA).
• Embedded test strategies including self-test and on-line test techniques.
• State-of-the-art solutions in embedded test for converters and PLL’s.

Who Should Attend

Technicians, engineers and managers involved in design, testing or reliability of SoC and SiP based mixed signal systems including:

• Design engineers
• Test engineers
• Reliability engineers
• Yield analysis engineers
• Product engineers
• FA engineers
• Application engineers

Prerequisite

Participants should have a basic background and understanding of semiconductor technologies and some circuit design basics. Analogue design and engineering expertise will not be assumed as a optional tutorial in analogue engineering will be made available. Previous familiarity in the design and test engineering domain will be advantageous in maximizing the impact of the course on the participant. Nonetheless crucial concepts will be reviewed as needed.

Course Methodology

This course is presented in an interactive classroom style utilizing lecture, open discussion, and examples.

Course Duration 3 or 4 days or 1 day extended tutorial (3 day version will not feature class excercises).

Course Structure

DAY 1:

Mixed Signal DfT fundamentals:

• Roadmaps and trends in DfT
• SoC and SiP test challenges
• Basics behind DfT
• Practical Measurement Techniques
• Fault modeling and FMEA processes

Day 2

System Level DfT:

• Mixed Signal test specifications
• Mixed Signal measurement and test techniques
• Digital DfT strategies for Mixed Signal Applications
• Test Access & Control architectures
• DfT solutions for high speed interfaces
• Gain control and filter DfT solutions
• On-chip signal generation and response analysis
• On-line test strategies

Day 3

Converter & PLL Design for Testability Strategies:

• Roadmaps and trends in converter and PLL embedded test
• Test specifications across application domains
• Conventional test strategies & DfT approaches
• Test time, outgoing quality and measurement challenges

Day 4 :

Converter & PLL embedded Test Strategies:

• Embedded tester strategies for converter & PLL test
• Partial & Full Self-Test
• Embedded Test for High Resolution Converters
• Self Calibration, Self Repair and Fault Tolerance Concepts