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Synopsis

This course can be taken as a full 4 day course or a 3 day version that does not include the practical sessions, The material is organised such that delegates only interested in attending specifics components of the course can attend single days only if necessary.

Design for Testability (DfT) is fundamental to digital system design. In modern chips, the handling of high volumes of test data requires the integration of test access and control structures for logic, cores, memory and interfaces. A variety of test strategies must be supported through these structures to ensure manufacturability. Furthermore to ensure that defects in nanometer devices and interconnect infrastructure are caught and variability in process is handled to prevent yield problems. The move to Built-in Self-Test continues and the emergence of 3D systems continues. Both presents new challenges to the design and test communities.

The first 2 days of this course will focus on the basic knowledge needed to be effective as a Design for Test engineer. The trends in Test Engineering will be discussed with specific reference to the International Technology Roadmap for Semiconductors and the iNemi roadmap. The basics of test will be covered including fault models and test methods and the basic legacy DfT architectures covered that today’s DfT techniques are based upon. The application of these basic architectures to SoC test will then be covered including DfT structures to support at-speed and delay testing, memory test and high speed interface testing. Built-in Self-Test will be addressed in detail and power consumption and management issues during the test process will be explored.

The second 2 days will focus on the use of IEEE test standards within SoC and SiP designs and in particular the implications of nanometer design and 3D integration on the use of these standards. Aiming to deliver high quality and economic test programs. A practical session will be included to instruct students on the integration of test wrappers for embedded cores. IEEE 1149, 1500 and emerging standards including 1687 will be addressed together with IEEE 1149 extensions. Variability in modern processes and the implications on test will also be addressed as will practical test issues including signal coupling, noise and instrumentation awareness.

What You Will Learn

  • International trends in Design for Test Engineering
  • Digital Test strategies and methods
  • Fundamental Digital Design-for-Test structures based around scan
  • Fault models used within nanometer CMOS
  • Design for testability functions to support delay, IDDQ and high speed interface test
  • Memory test methods and Built-in Self Test architectures
  • Use of IEEE standards in SoC test
  • Handling variability within the test process
  • Practical Signaling and measurement issues
  • Test implications associated with 3D Integration and heterogeneous systems (MEMS, analogue and Bio integration)

Who Should Attend

Technicians, engineers, circuit designers, and managers involved in design, testing or reliability of SoC and SiP based systems including:

  • Design engineers
  • Test engineers
  • Reliability engineers
  • Yield analysis engineers
  • Product engineers
  • FA engineers
  • Application engineering

Prerequisite

Participants should have a basic background and understanding of semiconductor technologies and the basics of logic design and synchronous digital system design. No prior knowledge of digital test is required

Course Methodology

This course is presented in an interactive classroom style utilizing lecture, open discussion, and examples.

Course Structure

DAY 1: Digital Test fundamentals

  • Roadmaps and trends in Digital Test for System on Chip
  • Test generation & compression techniques
  • Fault models and test methodologies
  • Scan fundamentals

DAY 2: Design for Testability

  • Delay and Power Aware Test
  • IDDQ test
  • Memory Test
  • High Speed Interface Testing
  • Built-in Self Test

DAY 3: System Level Test Access

  • IEEE test access and control standards
  • 1149.1 Boundary Scan
  • 1500 Core Test
  • 1149 variants and emerging standards (inc. P1687)
  • Practical exercise

Day 4: Towards 3D & Mixed Signal Test

  • Test Challenges for System-in-Package and 3D technologies
  • Signals and Measurement
  • Handling Variability
  • Handling heterogeneous technologies

Instructor Profile

Prof. Andrew Richardson

Professional Qualification and Experience

Professor Andrew Richardson holds a personal chair at Lancaster University in Microsystems Engineering. He is a specialist in Design for Test and Reliability Engineering. Professor Richardson’s research background has been based firmly around advanced test methods for state of the art chips and included work on defect oriented testing, especially IDDQ, Self-Test with a focus on Converters and PLL’s and on-line test strategies. This research portfolio has been delivered with industrial partners from the European Union including AMI Semiconductors, ST Microelectronics, Philips, NXP and Dolphin Integration. Between 2004 and 2010 this portfolio was integrated into a new European Network of Excellence in Design for Manufacture Technology for Micro & Nano based systems that involved 24 partners across Europe. Prof. Richardson coordinated this venture that aimed to extend Design for Test Engineering to emerging technologies and deliver on-line as well as off-line test strategies.

Prof. Richardson has delivered both conventional and distance learning professional courses in the area of design for testability through ISLI, Livingston and Europractice as well as a number of private industrial clients including NOKIA, Wolfson Microelectronics and NMI and in Process Awareness and IDDQ test through what was previously Philips Semiconductors.

Prof. Richardson contributes actively to international dissemination events including work on the steering committee of the IEEE International Mixed Signals, Systems & Sensors Test Workshop, (http://cadlab.ece.ucsb.edu/IMS3TW2011/) (chairman in 2006) and program committees for the European Test Symposium (http://www.ieee-ets.org/) and Design, Test Integration and Packaging – DTIP (http://cmp.imag.fr/conferences/dtip/dtip2011/) as well as the European Workshop on Microelectronics Education (EWME). Prof. Richardson was also guest editor on special issues in mixed signal test in 2007 for both the Springer Journal in Electronic Test Technology and Applications and the Elsevier Microelectronics Journal.

Professor Richardson is also now the Managing Director of enablingMNT, UK that is part of the enablingMNT group with partner offices located in Holland and Germany. Besides test engineering and education, Prof. Richardson counts among his interests: mountaineering, skiing and playing the guitar.

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